The phase change memory (PCM) is a type of non-volatile random-access memory and includes an array of PCM cells arranged on the cross-points of the word lines in row and the bit lines in column. The respective PCM cells have an activation region made of the phase change material capable of being switched between an amorphous and a crystalline state by heating the memory cell. Usually the amorphous and the crystalline states respectively have different detectable characteristics, such as the resistance or the electrical resistivity, so as to provide a distinguishable scale between both states to store the binary information in the respective PCM cells.
FIG. 1 presents a common behavior of a phase change memory (PCM) cell, wherein each curve presents the current profile vs. the resistance value. FIG. 1 shows that if the PCM cell has a higher resistance, then the PCM cell correspondingly has a higher threshold voltage (VTHS).
In order to reset the PCM cell, a high voltage which is higher than VTHS must be provided. Such a step, which is usually referred to as breaking down the cell, results in a high current on the PCM cell path to generate heat for melting the PCM material.
However, in any time, if a voltage is close to VTHS is accidentally applied to the bit line (BL), the cell might be disturbed. Therefore, a conventional way of sensing is usually to apply a relatively low voltage to the bit line.
Such a low sensing voltage on the bit line is appropriate if the multi-level cell (MLC) or the margin check is not concerned. As shown in FIG. 2, in which the solid line and the dotted line respectively represent the current value on the low and high resistance PCM developed by the applied BL voltage, the two turns of the dotted line show the aforementioned breaking down when the applied voltage is too large. Under such a condition, the dotted line represents a profile turning from the high resistance to the low resistance. According to FIG. 2, when a voltage is applied to the BL, the window between the two current generated by the high and low resistance PCM is large, and thus the reference for differentiating between the two current can be placed at any point inside the window.
FIG. 3 illustrates the suffered difficulty when a data reading process is performed on a high resistance PCM cell for a multi-level cell (MLC) and a margin check. For example if the PCM cell has a 2.1 mega-ohm resistance, the reference resistance is 2 mega-ohm and in the mean time the read bit line voltage is assumed 0.4V, then the obtained cell current is 190 nA and the reference current is 200 nA. Subject to the condition, it is difficult to precisely distinguish such a minor current difference.
It is therefore attempted by the applicant to deal with the above situation encountered in the prior art.